| Summary: | 碩士 === 國立臺北科技大學 === 電力電子產業研發碩士專班 === 98 === Generally, the end-to-end communication of network is completed with microprocessor using RISC to move those packets, even though it needs large flash memory and works slowly. A FIFO is utilized to solve the numerous memories, but the transmitting speed is still slow and needs to be improved. Moreover, replacing the microprocessor with DRR is proposed to have good throughput by checking the packets.
In this thesis, the DRR is completed with Verilog hardware description language. As the packets need to be transmitted, they need to be judged according to their sizes using the DRR mechanism. The destination is to reduce the waiting time and to decrease the loss rates. In addition, a traffic management is presented to have a fair distribution of bandwidth for the packets. Finally, the efficient fair queuing with DRR is implemented with FPGA.
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