VLSI Architecture Design of Low Power and Low Latency Turbo Decoder
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 98 === This thesis proposed a low power and low latency VLSI architecture for turbo decoder. Three methods are used to improve the latency of turbo decoder, and reduce the sliding windows ram to save power. In our design, we proposed a novel dummy beta free turbo dec...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/a5xr3k |