VLSI Architecture Design of Parallel Phase Turbo Decoder
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 98 === In this thesis, we proposed a novel parallel phase turbo decoding algorithm for VLSI architecture. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce a long decoding latency. The proposed algorithm ex...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9w5pyu |