A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER
碩士 === 大同大學 === 電機工程學系(所) === 98 === The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enabl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/11343049141724638485 |