A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER

• Main Authors: Chia-ching Lin, 林嘉慶
• Other Authors: Ming-chieh Tsai
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/11343049141724638485

碩士 === 大同大學 === 電機工程學系(所) === 98 === The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enables the use of single -stage cascade amplifier. In addition, it produces the first bit from this sample and hold circuit to reduce one stage sub-ADC. In order to reduce power dissipation, opamp-sharing technique is implemented as well. Based on result of simulation by HSPICE, this ADC achieves 9.1 bits ENOB at 75MHz, DNL -0.48~+0.5LSB and -0.7LSB~+0.75LSB with power supply 1.8V and 200MHz sampling rate, the overall power dissipation is 73mW and FOM is 0.66 pJ/conversion. Total active area is 0.994 x 0.854 mm2 in 1P6M 0.18μm CMOS process