A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER
碩士 === 大同大學 === 電機工程學系(所) === 98 === The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enabl...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2010
|
Online Access: | http://ndltd.ncl.edu.tw/handle/11343049141724638485 |
id |
ndltd-TW-098TTU05442023 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-098TTU054420232016-04-22T04:23:28Z http://ndltd.ncl.edu.tw/handle/11343049141724638485 A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER 應用於高解析度影像之管線式類比數位轉換器 Chia-ching Lin 林嘉慶 碩士 大同大學 電機工程學系(所) 98 The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enables the use of single -stage cascade amplifier. In addition, it produces the first bit from this sample and hold circuit to reduce one stage sub-ADC. In order to reduce power dissipation, opamp-sharing technique is implemented as well. Based on result of simulation by HSPICE, this ADC achieves 9.1 bits ENOB at 75MHz, DNL -0.48~+0.5LSB and -0.7LSB~+0.75LSB with power supply 1.8V and 200MHz sampling rate, the overall power dissipation is 73mW and FOM is 0.66 pJ/conversion. Total active area is 0.994 x 0.854 mm2 in 1P6M 0.18μm CMOS process Ming-chieh Tsai 蔡明傑 2010 學位論文 ; thesis 86 en_US |
collection |
NDLTD |
language |
en_US |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 大同大學 === 電機工程學系(所) === 98 === The thesis describes the implementation of a 10-bit 200Msampe/s pipelined A/D converter with merged-mode sample and hold circuit which is built in comparator and decoder. The advantage of this architecture is to reduce the signal swing requirement, thus, it enables the use of single -stage cascade amplifier. In addition, it produces the first bit from this sample and hold circuit to reduce one stage sub-ADC. In order to reduce power dissipation, opamp-sharing technique is implemented as well.
Based on result of simulation by HSPICE, this ADC achieves 9.1 bits ENOB at 75MHz, DNL -0.48~+0.5LSB and -0.7LSB~+0.75LSB with power supply 1.8V and 200MHz sampling rate, the overall power dissipation is 73mW and FOM is 0.66 pJ/conversion. Total active area is 0.994 x 0.854 mm2 in 1P6M 0.18μm CMOS process
|
author2 |
Ming-chieh Tsai |
author_facet |
Ming-chieh Tsai Chia-ching Lin 林嘉慶 |
author |
Chia-ching Lin 林嘉慶 |
spellingShingle |
Chia-ching Lin 林嘉慶 A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
author_sort |
Chia-ching Lin |
title |
A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
title_short |
A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
title_full |
A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
title_fullStr |
A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
title_full_unstemmed |
A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER |
title_sort |
10-bit 200ms pipelined adc for high defination video decoder |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/11343049141724638485 |
work_keys_str_mv |
AT chiachinglin a10bit200mspipelinedadcforhighdefinationvideodecoder AT línjiāqìng a10bit200mspipelinedadcforhighdefinationvideodecoder AT chiachinglin yīngyòngyúgāojiěxīdùyǐngxiàngzhīguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT línjiāqìng yīngyòngyúgāojiěxīdùyǐngxiàngzhīguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT chiachinglin 10bit200mspipelinedadcforhighdefinationvideodecoder AT línjiāqìng 10bit200mspipelinedadcforhighdefinationvideodecoder |
_version_ |
1718230891272077312 |