DESIGN AND IMPLEMENTATION OFA 5.8-GHz PHASE-LOCKED LOOP CIRCUITS
碩士 === 大同大學 === 電機工程學系(所) === 98 === This thesis presents a 5.8-GHz PLL design based frequency synthesizer for wireless commutation system. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, a LC-tank VCO, an injection-locked frequency divider and a frequ...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12253673350045117480 |