Congestion-aware Programmable Logic Device Routing Framework for Area-efficient Switch Architectures
碩士 === 元智大學 === 資訊工程學系 === 98 === Dangling-wires in area-efficient switches incur excessive routing congestiton as well as wire capacitance. In this thesis, we propose a routing framework to reduce the number of dangling-wires in crossbar switch block. Our routing framework consists of pattern routi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55894536594495131145 |