Congestion-aware Programmable Logic Device Routing Framework for Area-efficient Switch Architectures

• Main Authors: Yi-Huang Hung, 洪郼艎
• Other Authors: Yi-Yu Liu
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/55894536594495131145

碩士 === 元智大學 === 資訊工程學系 === 98 === Dangling-wires in area-efficient switches incur excessive routing congestiton as well as wire capacitance. In this thesis, we propose a routing framework to reduce the number of dangling-wires in crossbar switch block. Our routing framework consists of pattern routing, anchor pair insertion, bounding box expansion, and advanced bounding box expansion. The experimental results demonstrate that our proposed router reduces dangling-wires and channel width by 19% and 38%, respectively, as compared to VPR-C. Besides, the wire length is reduced by 11%. By using our new routing graph model, the run time of our new router is 20X over VPR-C. Furthermore, we extend the crossbar switch architecture to a mixed SRAM-based switch block with higher area-efficiency as compared to a conventional universal switch block. We address new routing issues raised by the new area-efficient switch block.