A Wide-Range All-Digital Duty-Cycle Corrector with Output Clock Phase Alignment in 65nm CMOS Technology
碩士 === 國立中正大學 === 資訊工程研究所 === 99 === A Wide-Range All-Digital Duty-Cycle Corrector (ADDCC) with Output Clock Phase Alignment in 65nm Technology is presented in this dissertation. In high speed data transmitter application, such as double data rate (DDR) SDRAM and double sampling analog-to-digital co...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59047555443971297202 |