| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 99 === A Wide-Range All-Digital Duty-Cycle Corrector (ADDCC) with Output Clock Phase Alignment in 65nm Technology is presented in this dissertation. In high speed data transmitter application, such as double data rate (DDR) SDRAM and double sampling analog-to-digital converter (ADC), the positive edge and the negative edge of system clock are utilized for sampling the data. Thus, theses systems require an exact 50% duty-cycle of system clock. Nevertheless, system clock is affected by the unbalanced rise time and fall time of the clock buffers with process, voltage and temperature (PVT) variations, which cause error data latching when clock duty-cycle is not equal to 50%. We summarize some researches and architectures in prior years, moreover, discuss these differences and how to improve them. In this thesis, we use all-digital control method not only speed-up locking time than voltage control method, but also solve the leakage current problem of the voltage charge-pump control. Besides, we presented the novel high resolution ADDCC which can solve the restricted resolution of time-to-digital converter (TDC). The half-cycle delay line (HCDL) generates output clock signal by another mirror circuit will cause mismatch problem in nano-meter CMOS process when there has on-chip variations (OCVs). The proposed ADDCC is implemented on a standard performance (SP) 65nm CMOS process with standard cell library, and verify the performance of the proposed circuit.
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