Metal/SiO2/Y2O3/SiO2/Si TFTs Memory Device Using High-k Y2O3 Charge Trapping Layer deposited by E-gun

• Main Authors: Jie Ting Luo, 羅介廷
• Other Authors: T. M. Pan
• Format: Others
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/56246886247119819440

碩士 === 長庚大學 === 光電工程研究所 === 99 === In this thesis, we use physical vapor E-gun method deposited high-k dielectric for nanocrystals trapping layer. A 10-nm direct tunneling oxide was deposited using an electron gun system by yttrium oxide (99.9% pure) powder. After various temperature RTA 600,700,800oC in N2 ambient, we found that Y2O3 film will be self-assemble with increasing annealing temperature up to 700°C in N2 ambient. Although the trapping layer annealed in N2 at 700°C a larger C-V shift, we can find that Y2O3 devices with 500oC and 600oC have better film quality. In chapter 3, we used the same method to deposite the trapping layer of TFT memory. We can use gate injection mechanism to program and erase charge (by +15V program and -15V erase) .The memory window is about 3.4 voltage, and the ON/OFF current ratio achieve about 6 order. The device characteristic is similar to capacitor which we previous made. RTA 600oC obtained better film quality and 700oC achieve good capacitor characteristic, respectively. We prove that Y2O3 trapping layer on TFT memory has optimum value below RTA 600oC. We suppose that using another way to make blocking under temperature 600oC, not only receive better blocking oxide quality but also use FN or CHE mechanism to program and erase. In the future, we can obtain optimum Y2O3 TFT memory even do without additional RTA process.