Fast locking PLL with all-digital locked-aid circuit
碩士 === 長庚大學 === 電機工程學系 === 99 === To design a PLL must concern several conditions as the following: low jitter, low power consumption and fast-locked. According to the design of PLL model must deal with a trade-off between the locking time and the bandwidth. The thesis presents a lock-aid circuit to...
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| Format: | Others |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61849136471049242475 |