Clock Network Power Reduction Using Multi-bit Flip-Flops in Multiple Voltage Island Design
碩士 === 中原大學 === 資訊工程研究所 === 99 === Power consumption is an important issue in modern high-frequency and low power design. Multi-bit flip-flops are used to reduce the clock system power. The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption. In this pa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69698640747510308266 |