A Low Power Radix-4 Booth Multiplier Design
碩士 === 國立中興大學 === 資訊科學與工程學系所 === 99 === In this paper, we present a low power Booth multiplier with a conditionally gated decoder. Using the features of Booth decoding, our design can reduce the unnecessary node switching in Booth decoder. Based on UMC 90-nm CMOS technology, simulation results show...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26398031568419386105 |