Clock Tree Optimization with Prebond Testability in 3D IC

Clock Tree Optimization with Prebond Testability in 3D IC

碩士 === 中興大學 === 資訊科學與工程學系所 === 99 ===

Bibliographic Details
Main Authors:	Yu-Chang Hung, 洪毓章
Other Authors:	王行健
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/40070693331296618063

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