| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 99 === Because the mobility of LTPS (low temperature polycrystalline silicon) TFTs (thin film transistors) is larger than that of amorphous silicon TFTs, LTPS TFTs have widely used in the new generation display. Therefore, to investigate the reliability of LTPS TFTs is a very important issue. When LTPS TFTs are used as driving components, they are operated by AC signal on both gate and drain terminals. When the TFTs normally work, they would be toggled into both On/Off regions. From the results of experiments, we could find that the TFTs operated in the Off region had larger degradation than those operated in the On region. Thus, in this thesis, we will study the reliability of the LTPS TFTs worked in Off region.
In the first part, we investigate the relationship between stress time and the degradation of N-type poly-Si TFTs stressed by AC signal on the gate and drain. For the synchronous signals, we find that LTPS TFTs operated in Off region exhibit larger degradation, and then further investigate the relationship between the device reliability and both gate and drain are normal mode waveforms (condition 1). From the experimental data, we find that the degradation of poly-Si TFTs increase as frequency increase (as a result of AC signal oscillation increase). The rising time of the gate AC signal dominates the degradation characteristic of N-type poly-Si TFTs which operated in Off region. Under complement AC gate bias stress and normal AC drain bias stress (condition 2), we also find that the degradation of poly-Si TFTs increases as frequency increase. But falling time of the gate AC signal dominates the degradation characteristic. The degradation of the LTPS TFTs under condition 2 is more than that under condition 1. We propose the degradation mechanisms for LTPS TFTs under AC stress in Off region, and adopt the FR-IV measurement to verify the degradation mechanisms. For the asynchronous signals, we find that the more delay of the gate signal we apply, the more the degradation is. We use the quantitative method to analyze these degradation phenomena.
In the second part, we study the relationship between stress time and the degradation of N-type poly-Si TFTs under DC stress in Off region. From the experimental data, we find that maximum transconductance and on current increase at first and then decrease except Vg =0V. The larger magnitude of the negative gate voltage we apply, the more maximum transconductance and on current increase we obsevered. maximum transconductance and on current increase because of the channel shortening effect. Finally, we proposed the degradation mechanism for LTPS TFTs under DC stress in Off region. We used FR-IV、C-V、sampling current measurements to verify the degradation mechanism.
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