A Low Power 12-bit 100KSample/s Successive- Approximation Analog-to-Digital Converter
碩士 === 國立暨南國際大學 === 電機工程學系 === 99 === In this thesis, A low power 12-bit 100KSample/s successive-approximation(SAR) analog-to-digital converter(ADC) is presented. The ADC contains a sample and hold circuit(S/H), a digital-to-analog converter(DAC), a latched comparator, and a successive-approximation...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09580713306729557654 |