| Summary: | 碩士 === 國立交通大學 === 材料科學與工程學系奈米科技碩博士班 === 99 === In order to increase the gate control capacity on the channel, multi-gate structure has been extensively studied as the critical dimension of thin-film transistors (TFTs) is scaled down. Both gate-all-around (GAA) TFTs and TFT SONOS memory devices have been demonstrated previously with excellent channel controllability and outstanding memory properties. On the base of previous research, polysilicon nanowire transistors with Ω-Gate have been proposed in this study. The Ω-Gate structure exhibits good controllability on channel presumably due to the coverage of four corners of device channel. Moreover, an asymmetric gate structure by converting one side of Ω-Gate into Tri-Gate such that lower leakage current and off state current enhanced.
A comparison on the characteristics of both Ω-Gate devices and asymmetric Ω-Gate device were performed. It is found that changing the ratio of asymmetric structure can effectively change the device characteristics. When in high proportion of asymmetric structure, the device characteristics close to the Tri-Gate, and for low proportion of asymmetric structure, devices exhibit characteristics like Ω-Gate devices which possess properties including a high driving current, a steep subthreshold swing, a high on/off current ratio, low gate induced drain leakage (GIDL),and short channel effect suppression(SCE). The proposed asymmetric gate devices, combining Tri-gate and Ω-Gate, successfully inhibit the leakage current and suppress off-state current, and enhance the overall electrical properties.
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