Development of metal-assisted nano-stacks and their applications in high performance TFT-NVM

• Main Authors: Wang, Tai-Jui, 王泰瑞
• Other Authors: Kuo, Cheng-Tzu
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/94222535634588058666

博士 === 國立交通大學 === 材料科學與工程學系 === 99 === This work was to develop various metal-assisted nano-gate stacks on Si wafer, including SiO2/Ir-NCs/SiO2/Si-Sub, SiO2/Ir-NCs/Si3N4/SiO2/Si-Sub, SiO2/Ir-silicide- NCs/SiO2/Si-Sub, SiO2/Ir-NCs/SiO2/Si3N4/Poly-Si, SiO2/Ni-NCs/Si3N4/SiO2/Poly-Si, SiO2/Si3N4/Ni-NCs/Si3N4/SiO2/Poly-Si, SiO2/Si3N4/SiO2/Poly-Si, and Al2O3/Si3N4/ Ni-NCs/Si3N4/SiO2/Poly-Si stack structures. The aims were to use for thin film transistor- nonvolatile memory (TFT-NVM) applications. The metals, including Ir, Ir-silicide, and Ni nano-dots, were deposited by PVD and followed by rapid thermal annealing or hydrogen plasma pretreatments. The other layers of the stacks were deposited by CVD or PVD, and followed by defining device components through lithography processes. The process parameters consist of 3-D size distribution of metallic dots in the stack, layer thickness and material, tunneling layer engineering, pretreatment temperature and time. Each layer structures and stack properties were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS), capacitance-voltage (C-V) and current-voltage (I-V) measurements. By comparing Ir-assisted “SiO2/ Ir-NCs/ SiO2/ Si-Sub” and “SiO2/Ir-NCs/Si3N4/SiO2/Si-Sub” gate stacks, the results show that performance by tunneling engineering through using asymmetrical Si3N4/SiO2 bi-layer is much better than SiO2 single-layer, in terms of program/erase (P/E) efficiency and memory window size (from 8.1 V up to 12.6 V at +/- 10 V sweeping voltages), with only 5% degrade in data retention and no significant degrade in device endurances up to 104 cycles under P/E stressing condition of +/- 9 V, 100 ms. This is due to the fact that the function of asymmetrical bi-layer is essentially a two-step tunneling action to tunnel electrons into the trapping centers through one high barrier and a slight lower barrier in comparison with one step action through one high barrier under the same total tunneling distance. By comparing Ir-silicide-assisted “SiO2/Ir-silicide-NCs/SiO2/Si-sub” gate stack with Ir-assisted asymmetrical stack, the results have demonstrated that the former stack has a wider memory window (i.e. 14.2 V at sweeps of +/- 10 V can be reached) but less data retention ability (about 78% degrade) than the latter stack. Furthermore, the trap density of the former stack is estimated to be about 1.06×1013 cm-2, indicating a high trapping efficiency stack for nonvolatile memory application. About performance of Ir-NCs-assisted thin film transistor nonvolatile memory (TFT-NVM) devices with Ir-NCs lying on Si3N4/SiO2 asymmetric tunneling layer, the results indicate that a significant memory window of 5.5 V can be obtained even under a thicker tunneling layer thickness (Si3N4/SiO2 = 5 nm/5 nm) than the other previous discussed stacks. Furthermore, after 104 s retention time, the memory window can be maintained up to 4.0 V, which is more than enough to act as logic states. This may take advantages of asymmetric tunneling layer, and the number density of Ir-NCs is within the optimum range as proposed in the literature (in this case, ~ 6 x 1011 cm-2 with particle diameters ranging from 4 to 12 nm). The Ni-NCs can be successfully fabricated under 450oC, which is much lower than temperature tolerance 600oC of glass substrate for low temperature poly-silicon TFT-NVM application. This may be due to applications of H-plasma pretreatment and Ni material for NCs formation. Furthermore, the number density of ~ 5×1011 cm-2 of Ni-NCs is close to the proposed optimum range. The results also indicate that the window size of ~ 1.1 V after 104 s retention time can be reached, which is good enough but less than the values of previous stacks due to a lower work function of Ni material and thinner tunneling layer. By examining thickness effect of Si nitride layer, the results demonstrate that the stacks with thinner nitride thickness (< 5 nm) and without NCs show no detectable window size. In other words, a thinner nitride layer has no significant charge trapping ability, i.e. can act as a tunneling layer. The results also indicate that a thicker nitride layer (about 15 nm) could be used for charge trapping layer due to its great defect density. Therefore, a window size of 2.0 V under a P/E condition of +/- 18 V for 1 sec could be obtained by a trade-off of P/E efficiency. An addition of Ni-NCs in the stack (i.e. SiO2/Si3N4/Ni-NCs/Si3N4/SiO2/Poly-Si) appeals able to further increase window size up to 3.2 V under the same P/E conditions. In addition to good trapping ability of NCs, it may be due to more hetero-interfaces between Ni-NCs/Si3N4 further offering more charge trapping centers. By comparing the following gate stack, effect of changing the blocking layer of the stack to become tunneling layer by replacing thicker SiO2 layer (~ 15 nm) with thinner Al2O3 layer (~ 5 nm) was examined, designing stack with gate injection employing Fowler-Nordheim tunneling mechanism. The results indicate that the Ni-NCs assisted metal-alumina- nitride-oxide-silicon-TFT could greatly reduce the P/E voltages (window size of 4.2 V under -10 V and +8 V), and maintain acceptable data retention ability (memory window of 1.6 V after 104 s). This design idea is essentially to enhance the tunneling ability through changing material without significant reducing the retention ability. In summary, this work examines basically the performance of the stacks with two classes of processing temperature (< 500oC or ~ 900oC), which can be an advantage for fabricating 3-D stack NVM. The tunneling and trapping layer engineering, including asymmetrical structure, gate injection scheme, gate dielectric material, metal-NCs material, and layer thickness, can be used to design different devices for different NVM applications.