Asynchronous Packet-switched Network-on-chip: Protocol and Architecture
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 99 === In recent years, the number of computing resources in a single chip has been enormously increased. The complexity of design is proportional to the number of cores. In order to reduce the design complexity and increase the re-usability of the IP blocks, designe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66964965220754005835 |