Clock Power Minimization with Maze Routing-based Merging in Multi-Bit Flip-Flop Synthesis
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 99 === Low-power has become an important issue for modern designs. In a digital design, the power consumption can be reduced by merging several one-bit flip-flops (FFs) into one multi-bit flip-flop (MBFF) due to the decrease of used inverters. On the other hand, the...
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| Format: | Others |
| Language: | en_US |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/77839390378139030755 |