| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === As compared with two-dimensional (2D) ICs, three-dimensional (3D) integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, to minimize the number of TSVs becomes important in the design processes. Therefore, in this thesis, we propose two iterative layer-aware 3D partitioning algorithms, named iLap-2 and iLap-k, for TSV minimization. iLap-2 iteratively applies 2-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap-2 also properly fulfills a special I/O pad constraint incurred by 3D ICs to further improve its outcome. Based on iLap-2, iLap-k replaces the 2-way partitioning by k-way partitioning engine for considering the distribution of the future. The experimental results show that iLap-k can reduce the number of TSVs by about 33% as compared to several existing methods. Besides, iLap-k distributes TSVs more evenly among different vertical layers, preventing any layer junction from having a burst number of TSVs. That is important to application specific integrated circuit (ASIC) as well as regular structures.
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