Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay
碩士 === 國立交通大學 === 電子研究所 === 99 === The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA arch...
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05911280876636815748 |