Design-for-Debug Aware Layout Modification for FIB Net Observation and Circuit Editing
碩士 === 國立交通大學 === 電子研究所 === 99 === Failure analysis}(FA) plays a critical role in today's silicon debugging flow. The efficiency of FA depends on how many net values can be observed while a chip is running. If we acquire more net values, locating the failure will become easier. On the contrary,...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43526530218290833872 |