Design-for-Debug Aware Layout Modification for FIB Net Observation and Circuit Editing

• Main Authors: Chang, Tsung-Wei, 張琮偉
• Other Authors: Jou, Jin-Yang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/43526530218290833872

碩士 === 國立交通大學 === 電子研究所 === 99 === Failure analysis}(FA) plays a critical role in today's silicon debugging flow. The efficiency of FA depends on how many net values can be observed while a chip is running. If we acquire more net values, locating the failure will become easier. On the contrary, few values of nets would result in more difficult FA. In modern techniques of FA, focus ion beam is widely used since it can directly observe net values and modify chips. These characteristics enhance the efficiency of FA. However, due to the advanced technologies, both the interval between each wire and width of wires become smaller. This phenomenon causes that observing and modifying arbitrary nets become more difficult. Thus, difficulty of FA will raise as well. To conquer this problem, we propose a methodology to modify the routing of a design in advance. In this manner, we can reach the goals: enhancing the (1)observing rate and (2)modifying rate. Our experimental results show that the improvement of observing rate reaches 50% on average and modifying rate doubled compared with the original design.