| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === Lifetime reliability is one of the key design factors for robust VLSI systems. Bias Temperature Instability, Hot Carrier Injection, and Time Dependent Dielectric Breakdown have become major concerns for performance and yield of nano-scale CMOS VLSI systems. Static Random Access Memory (SRAM) plays a significant role in the System on Chip design. The conventional 6T SRAM cell faces severe challenges on reliability issues due to process variations and some device reliability effects. Among those effects, Bias Temperature Instability is the most important one for a robust SRAM design due to the features of SRAM operation.
In this thesis, we propose a NBTI/PBTI testing structure and measurement flow to analyze the reliability degradation in nano-scale CMOS SRAM. First, SRAM Ring Oscillator (SRAM RO) is presented for measuring NBTI/PBTI degradation. Then, we introduce an all-digital on-chip testing circuit for noise margin of 6T SRAM. This circuit can measure out the read static noise margin and write margin, and can make statistical measurement results. Both two measurement/monitoring circuits has been implemented in UMC 55nm SPRVT CMOS technology. Embedded SRAM ring oscillator can achieve the goal to detect 15% of frequency difference between ring oscillators. Array based measurement circuit for noise margin can provide a digital read-out circuit with 0.167mV resolution in LSB.
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