A Wide Capture Range PLL based on All-Digital Design
碩士 === 國立交通大學 === 電信工程研究所 === 99 === In this thesis we design an all-digital phase-locked loop (PLL) with ultra-wide capture range which spans from 1kHz to 1MHz. The ratio of the highest frequency to the lowest frequency is 1000 and there is no need for prior information of the input frequency. With...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22245960003117005005 |