A Low Jitter Delay-Locked-Loop Applied on DDR4 DRAM
碩士 === 國立中央大學 === 電機工程研究所碩士在職專班 === 99 === Abstract The motivation of this work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the development and breakthrough of the CMOS process technology...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92473998118756756804 |