| Summary: | 碩士 === 國立中央大學 === 電機工程研究所碩士在職專班 === 99 === Abstract
The motivation of this work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the development and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6Gbps~3.2Gbps. The stability of clock becomes an essential part of design. The delay-locked loop (DLL) offers better jitter and stability performance than the phase-locked loop (PLL). So, it is more regularly applied on DRAM as a synchronous circuit than PLL.
This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90nm technology with a nominal supply voltage 1.2V and I/O supply voltage 2.5V. The input frequency is at 1.6GHz. Peak to peak jitter 1.68ps with a quiet supply, and 18.68ps under random noise of 10MHz, +/-10% amplitude on the supply after regulator, which is less than 11.5% of output clock cycle. DLL power dissipation is 20.58mW. Chip area is 0.5625mm2.
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