| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 99 === As the process technology progresses, the design flow of VLSI circuits becomes more and more complicated. Although the enhancing technique makes the chip size reduce, the fabrication cost arises simultaneously. The difference between two dimensional（2D）and three dimensional integrated circuits（3D ICs）is that 3D ICs emphasize the vertical connection between layer and layer, which can certainly arise the chip density, implying that we can obtain the same design with lower cost. Besides, the die-stacking technology of 3D IC provides designs with different technologies on a chip and supports the application of heterogeneous integration.
In 3D IC architecture, the thermal and power noise problems affect the performance of the whole chip. In this thesis, we present a method to solve these two problems by simultaneously adding thermal TSVs（TTSVs）for thermal issue and decoupling capacitors（decaps）for power noise issue. Since the unit-area capacitance of a TTSV at the room temperature is equivalent to that of a decap, and the unit-area capacitance of a TTSV is arisen with increasing temperature, TTSVs have the abilities of dissipating thermal and reducing power noise. We model these two abilities into the proposed method. Without enlarging the area of floorplanning, the proposed method can maximize the reduction of the temperature and IR-drop using linear programming under the given target temperature and voltage. If the target temperature or voltage could not be achieved, the differences between the real temperature (voltage) and target temperature (voltage) will be reported.
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