Design and Implementation of High-Speed Multi-operand Decimal Adders
碩士 === 國立屏東商業技術學院 === 資訊工程系(所) === 99 === In this paper, we have proposed area-efficient decimal adders with three inputs. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient summations with three inpu...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/11474026460945298310 |