An Optimized Loop Bandwidth Technique for the 5GHz Wide band PLL Frequency Synthesizer Design
碩士 === 國立中山大學 === 資訊工程學系研究所 === 99 === This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18μm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency d...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08015322806314255647 |