Design of A Novel Mixed-Voltage-Tolerant I/O Buffer with High Reliability
碩士 === 國立中山大學 === 電機工程學系研究所 === 99 === This thesis is composed of two parts: a 3×VDD mixed-voltage-tolerant I/O buffer with 1×VDD CMOS standard device, and a PVT detector for 2×VDD output buffer with slew-rate compensation. In the first topic, a 3×VDD bidirectional mixed-voltage-tolerant I/O buffer,...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93756739148778233314 |