Study of a Novel Vertical Non-volatile Multi-Bit SONOS Memory
碩士 === 國立中山大學 === 電機工程學系研究所 === 99 === In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall space...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28098558437662952220 |