| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 99 === In view of the challenges encountered by CMOS scaling, it seems inevitable that a highly integrated system on chip (SOC) must start from low production yield, and then it takes tremendous time and effort to improve the yield to a reasonably high level. Three-dimensional (3-D) integration can provide a means to overcome the difficulties in the design and manufacturing of these SOC products. On the other hand, the yield rate is also an unsolved issue of 3-D integrated circuit (IC). To improve the yield rate of the 3-D IC, it is important to have the repair mechanism in the design. Unfortunately, so far, there is little research for 3-D IC repair. In our study, we can classify the 3-D repair into three types: (1) the redundancy is on-chip and the enabling circuit is also on the same chip; (2) the redundancy is on-chip but the enabling circuit is on another chip, and (3) the redundancy is on another chip and the enabling circuit can be on a third chip. From another perspective, introducing vertical interconnects, such as through-silicon via (TSV), makes it feasible to stack multiple bad dies, each failing some but not the same parts, to produce a good die stack. In other words, the IC can become usable in the 3-D form, by patching a bad die by other bad dies. To exercise the third type of the 3-D repair method, we focus a TSV-based repair method in this paper. We propose a method to achieve this by using a dual-TSV hardwired switch (DTHS). Each DTHS is composed of at most two TSVs and four bond pads, connected by front-side and backside redistribution layer (RDL) metal lines in an orthogonal or twisted pattern. The location to form the TSV can be programmed by a direct write process, such as laser drilling. This type of TSV has been shown to enjoy better cost-effectiveness, if its usage is limited to a certain amount, say, 250,000 per wafer. We incorporate the DTHS in the design under such a restriction and enable the built-in circuit to establish the intra-die routing. In order to be a 3-D reparable IC, the original design needs to be modified. We also propose a modification method from the system point of view. For a SOC or memory design, it may be already partitioned into several separable parts by functionalities or power domains. Each part has its individual power connections such that it can be independently turned on or off. The effort of the modification is minor, because the SOC is readily composed of modules with predefined functions and power supplies. The DTHS herein is used: (1) to shut off the power connections and (2) to disconnect signal paths from both failing and unused parts and redirect them to the functional parts among the stacked dies. The shutoff makes the 3-D repaired IC consume almost the same power and also helps to remove some failures, such as excessive leakage and interconnection shortage; the isolation completely shuns signal conflicts. Although the speed is degraded due to the extra load incurred by DTHS, our simulation in a 65nm process shows the delay time is within 350ps which may still be justifiable. The performance degradation turns out to be a necessary evil, since inherently the die stack has poorer thermal conductivity than its two-dimensional (2-D) counterpart.
Because the repair process is a post processing after the mass production, we think that 3-D repair should not influence the normal manufacture. The penalty of 3-D repair is that a new test flow is needed to sort out failing parts in the bad dies which may induce an extra testing cost. Since the manufacturing cost of the bad dies is already charged to and amortized by the good ones, the repair cost is the main concern when determining if a 3-D patched IC is worthwhile. To justify the concept of this paper, we use the SRAM test chip to do 3-D repair, and the measurement results show that 3-D repair is feasible. Even so, the 3-D repaired IC is deemed to be a transitional-period product. Nevertheless, it does help to shorten time-to-market and make the irreparable die profitable
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