A De-skew Clock Generator for Arbitrary Delay and An All-Digital Continuous Rate Wide-Capture Range CDR
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === This thesis contains two chips one is DLL the other is CDR implemented in standard CMOS technology. The delay locked loop (DLL) is widely used for high-speed memory interface circuits and clock multipliers to perform clock de-skew. The DLL offers two attract...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/27233767916835425898 |