A 9Gb/s AC Coupled Chip-to-Chip Receiver
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === Because of technology scaling in CMOS chips, the internal clock frequency becomes faster and faster. However, the off-chip I/O signaling speed has been scaling much more slowly. To design high speed transceiver becomes an important issue. This thesis int...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70790988460850084834 |