Wireline Backplane Transceivers in 65-nm CMOS Technology
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === In this thesis, three wireline backplane circuit systems will be demonstrated, including a 10 Gb/s Decision Feedback Equalizer (DFE), a 20 Gb/s Transceiver Chip-set, and a 40 Gb/s Transceiver Chip-set. They are all implemented in 65-nm CMOS Technology. First of...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59233645083334976486 |