| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === In this thesis, three wireline backplane circuit systems will be demonstrated, including a 10 Gb/s Decision Feedback Equalizer (DFE), a 20 Gb/s Transceiver Chip-set, and a 40 Gb/s Transceiver Chip-set. They are all implemented in 65-nm CMOS Technology.
First of all, in 10 Gb/s Decision Feedback Equalizer, it consists of an analog equalizer and a decision feedback equalizer with an adaptation loop. This circuit achieves BER < 10−12 for 211−1 PRBS in 80 cm FR4 channel, and consumes 31 mW with 1 V supply. Besides, the chip area is less than 0.1 mm2.
In 20 Gb/s Transceiver Chip-set, a 27−1 PRBS generator, an injection-locked PLL, and a 3-Tap feed-forward equalizer (FFE) are implemented in transmitter side. An adaptive analog equalizer and CDR are implemented in receiver side. This system achieves BER < 10−13 in a 60 cm FR4 channel, and consumes 310 mW and 190 mW with 1.2 V and 1.3 V supply in transmitter and receiver, respectively. The chip occupies 0.27 mm2 in transmitter and 0.32 mm2 in receiver.
Finally, in 40 Gb/s Transceiver Chip-set, we propose a delay-line-based feed-forward equalizer in both transmitter and receiver, and an adaptation loop is implemented in receiver. We mount transmitter and receiver chip on Rogers RO 4003 board with 20 cm transmission line, and the chip-set can achieve BER < 10−12 for 27−1 PRBS. This chip-set occupies 0.63 mm2 in transmitter and 0.66 mm2 in receiver, and consumes 135 mW with 1.2 V supply and 322 mW with 1.6 V in transmitter and receiver, respectively.
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