A Low Power 200MS/s, 10bit Pipelined Analog to Digital Converter
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === In high speed, medium-high resolution analog-to-digital converter (ADC), the pipelined architecture is the most common used. To reduce the power consumption, the capacitor-sharing technique is used in [1], [2], [3], [4]. Conventional capacitor-sharing technique...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69859920904783910934 |