Dual-Unit-Capacitance Split-Capacitor-Array SAR ADC Design and Analysis
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === This thesis proposes a dual-unit-cap split-capacitor array architecture for Successive Approximation Register Analog-to-Digital Converter (SAR ADCs) that further enhances the performance of conventional split-capacitor array architecture. The thesis also provide...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/88890990186216317754 |