| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === This thesis proposes a dual-unit-cap split-capacitor array architecture for Successive Approximation Register Analog-to-Digital Converter (SAR ADCs) that further enhances the performance of conventional split-capacitor array architecture. The thesis also provides a direct-switching logic which can reduce the operation time of each cycle in an SA period efficiently.
Under the constraint that mismatch between capacitors could not influence the resolution of ADCs, we minimize the size of the unit-cap of each cap-array group separately and calibrate the weights of capacitors digitally. Therefore, it requires less capacitor area and DAC settling time compared with conventional split-capacitor array architecture. Moreover, it still possesses the advantages of simple symmetrical layout and routing, which are especially important when mismatch is a concern.
Adapting the monotonic switching procedure, we propose a direct-switching SAR digital logic to reduce unnecessary idle time in each SA cycle, which greatly improves the sampling frequency, thus the circuit performance.
A 9 bit dual-unit-cap split-capacitor-array SAR ADC is fabricated using TSMC 90nm process, The ADC runs at 100MS/s with 566μW power consumption at 1.2V supply voltage.
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