The Analysis of Through Silicon Via (TSV) in 3D IC and Application on Power Integrity Design
碩士 === 國立臺灣大學 === 電信工程學研究所 === 99 === With the fast development of the integrated circuit, the techniques for packaging high-density chips in advanced high-speed system have hit the wall recently. Therefore, how to keep conforming to the Moore’s Law in 2D packaging is becoming more and more critic...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58682843885570481164 |