A Formal-Assisted Buffer Insertion and Gate Sizing Technique Considering Multi-Corner Multi-Mode Timing Constraints
碩士 === 國立臺灣大學 === 電機工程學研究所 === 99 === Interconnect delay in the routed circuit becomes dominant as process technology goes into deep submicron range. Buffer insertion is one of the most effective techniques to reduce the interconnect delay. However, when multiple operation modes and process corners...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/07272576564098710431 |