Hardware Design of High Efficiency and Non-memory AES-128/192/256 Crypto Core

• Main Authors: Lin Jun-Jian, 林竣堅
• Other Authors: Chen Rong-Jian
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/07526376264747217486

碩士 === 國立聯合大學 === 電子工程學系碩士班 === 99 === This paper presents the architecture design of a high efficient and non-memory Advanced Encryption Standard (AES) crypto core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (28) to Galois Field GF(((22)2)2) can significantly reduce the hardware complexity of the SubBytes Transformation (S-box). Besides, the on-the-fly key expansion function is used to replace the RAM-based, and the new on-the-fly key scheduler fully supports AES-128, AES-192 and AES-256. Moreover, resource-sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. Experiment results show that the AES core works at 76.93 MHz clock it takes about 33 clocks and 66 clocks to complete an AES-128 encryption and decryption, respectively. That is, the corresponding throughputs are 298.4 Mbps and 149.2 Mbps. The hardware cost of the AES design is about 4526 slices with 3-in-1 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN system chips due to its acceptable power dissipation. We have integrated the AES core and ARM processor to develop a demo system. In our demo system, the GUI interface establishes a good communication relationship between users and target devices.