Design of Multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS Technology
碩士 === 亞洲大學 === 資訊工程學系碩士班 === 99 === In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (STI) stucture based on the 65 nm baseline low-voltage CMOS technology by three-dimentsional Sentaurus process and device simulations. A optimized uniform electric filed distrib...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41798275984609977509 |