IC Design of an Analog Sum-Product Decoder for Regular LDPC Codes
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === In this thesis, we propose an analog sum-product decoder based on Low-Density-Parity-Check (LDPC) codes, and use Gilbert multipliers to realize the function of Sum-Product algorithm. Literatures show that the traditional LDPC decoders working at the probab...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/7xys7c |