| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === In this thesis, we propose an analog sum-product decoder based on Low-Density-Parity-Check (LDPC) codes, and use Gilbert multipliers to realize the function of Sum-Product algorithm. Literatures show that the traditional LDPC decoders working at the probability domain have a major demerit on the chip’s area. Therefore, we propose a non-splice Gilbert multiplier that can decrease the chip’s area for analog sum-product LDPC decoders.
We have implemented two (8, 4) LDPC Sum-Product decoders with TSMC 0.18μm 1P6M CMOS technology and operating at VDD = 1.8V. The first decoder core size is 0.1mm2 including 3932 transistor counts, and the throughput is 8.48Mb/s while power consuming 1.105mW. The second decoder modifies the former chip’s circuits so that has a smaller core size and less transistor counts. The core size of second decoder is 0.083mm2 including 2600 transistor counts, and the throughput is 16Mb/s while power consuming 0.939mW.
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