Analog IC Design of Min-Sum LDPC Decoder with the Stopping Iteration
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === The stopping iteration method is wildly used in digital decoder design; however, there are few analog decoders employ this method. Hence, we propose an analog min-sum decoder with stopping iteration method that has advantages on throughput, decoding performa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/v68u9t |