Analog IC Design of Min-Sum LDPC Decoder with the Stopping Iteration
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === The stopping iteration method is wildly used in digital decoder design; however, there are few analog decoders employ this method. Hence, we propose an analog min-sum decoder with stopping iteration method that has advantages on throughput, decoding performa...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/v68u9t |
| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === The stopping iteration method is wildly used in digital decoder design; however, there are few analog decoders employ this method. Hence, we propose an analog min-sum decoder with stopping iteration method that has advantages on throughput, decoding performance, and power consumption speed ratio. Our decoder is based on LDPC codes and the min-sum algorithm, and we use the current mode circuit to implement design. Experimental results show that our decoder can save 90% power consumption speed ratio compared with traditional decoder.
The proposed analog min-sum (32,8) decoder with stopping iteration method is implemented by using TSMC 0.18μm 1P6M CMOS technology. The core size is 0.64 mm2 with 20125 transistors. The operation voltage of our decoder is 1.8V and can achieve 216Mb/s throughput while power consuming 4.98 mW.
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